Press Center
 
Home About us Products Support Quality & Certification Career Contact us
• Power Management
    Linear Regulators
    Low Dropout Linear Regulators
    DDR Termination Regulators
    Shunt Reference Regulators
    Step Down Switching Regulators
    Switching Regulator
    Step-Up DC-DC Converter
    PWM Controller
    White LED Driver
    Supervisory Circuit
    Voltage Detection and System R
    USB Power Switch
    Power Factor Control
    Li-Battery Protection or Charg
    FET Bias Controllers
    Combo IC
    Inverting DC-DC Converter
• Amplifier / Comparator
    Audio Amplifiers
    Operational Amplifier
    Voltage Comparator
• Analog Switches
    Video Signal Switch
    Analog Multiplexers, Demultipl
• Hall ICs
• Special Application ICs
    Motor Controller IC
    Interface and Driver Circuit
    Telecommunication Circuit
    Melody IC
    Alarm /Sound Generator IC
    Remote Controller IC
    Television Circuit
    Leakage Current Detector
    Automotive IC
    A-D or D-A Converters
    Miscellaneous
    Radio and Cassette Recorder Ci
    Timer
    Mouse&Keyboard Controller
    Transient Voltage Suppressors
    Sense Monitor
    Video Filter
    ZCB snubber
• Logic
• TRANSISTORs
• MOSFETs
    JFET
    Power Mosfet
• TRIACs
• SCRs
• DIODEs
 
Home > Interface and Driver Circuit
UCA9517 Datasheet
  

LEVEL TRANSLATING I2C-BUS REPEATER

 

DESCRIPTION

 

The UTC UCA9517 is a CMOS integrated circuit that

provides level shifting between low voltage (down to 0.9 V) and

higher voltage (2.7V to 5.5V) I2C-bus or SMBus applications.

While retaining all the operating modes and features of the

I2C-bus system during the level shifts, it also permits extension of

the I2C-bus by providing bidirectional buffering for both the data

(SDA) and the clock (SCL) lines using the UTC UCA9517

enables the system designer to isolate two halves of a bus for

both voltage and capacitance. The SDA and SCL pins are over

voltage tolerant and are high-impedance when the UTC

UCA9517 is unpowered.

The UTC UCA9517 drivers are not enabled unless VCCA is

above 0.8V and VCC is above 2.5V. The EN pin can also be used

to turn the drivers on and off under system control. Caution

should be observed to only change the state of the enable pin

when the bus is idle.

The output pull-down on the B-side internal buffer LOW is set

for approximately 0.5V, while the input threshold of the internal

buffer is set about 80mV lower (0.42V). When the B-side I/O is

driven LOW internally, the LOW is not recognized as a LOW by

the input. This prevents a lock-up condition from occurring. The

output pull-down on the A-side drives a hard LOW and the input

level is set at 0.25×VCCA to accommodate the need for a lower

LOW level in systems where the low voltage side supply voltage

is as low as 0.9V.

 

FEATURES

 

* Voltage level translation from 0.9V to 5.5V and from 2.7V to 5.5V

* I2C-bus and SMBus compatible

* Active HIGH repeater enable input

* Open-drain input/outputs

* Lock-up free operation

* Supports arbitration and clock stretching across the repeater

* Accommodates Standard mode and Fast mode I2C-bus devices and multiple masters

* Powered-off high-impedance I2C-bus pins

* A-side operating supply voltage range of 0.9V to 5.5V

* B-side operating supply voltage range of 2.7V to 5.5V

* 5 V tolerant I2C-bus and enable pins

* 0 Hz to 400 kHz clock frequency

 (the maximum system operating frequency may beless than 400 kHz because of

the delays added by the repeater).

About us  |  Products  |  Contact us
Copyright 2011 UTC All received